High-speed serializer-deserializer (SerDes) circuits may use phase interpolator (PI) based clock and data recovery circuits (CDR) for optimum recovered clock positioning at receivers. These SerDes circuits may need a robust I/Q generation with minimal mismatch and a high performance phase interpolator circuit. I/Q generation, however, may have limited design choices. For example, I/Q generation by full-rate clock and subsequently dividing by 2 (e.g., half rate architecture) may face increased sensitivity to duty cycle error, whereas running the phased-lock loop (PLL) at twice the frequency for full-rate architecture and using divide-by-2 may be quite a challenge for transceivers targeting low power and running at data rates higher than 10 Gb/s.
Quadrature VCO based full-rate I/Q clock generation may suffer from large area and worse phase noise versus power consumption, and a high performance delay locked loop (DLL) may involve large area and more complexity. Phase interpolator circuits may include current-mode logic (CML) based PIs, which may be power hungry and may occupy a large area, thus cannot be scaled with digital CMOS technologies.